When I force the xtensa to wake with an external trigger, the same WDT reset happened. It was fully operational, and there were no error messages at the time deepsleep was triggered. To prove this, I ran a system without sleeping until it was reporting temperatures of nearly 50C, then let it sleep. When we graph our temperature readings, the trends show that above 40C the readings stop, and below 40C they restart.Ĥ0C is well within the operating temperature of both our sensor chip and the ESP32 module. The WDT resets are also associated with off-module (but on PCB) sensor readings that are over 40C - we haven’t seen this because the readings are lost. W (60) boot: WDT reset info: APP CPU PC=0x7677c9cfĭ (65) boot: WDT reset info: APP CPU STATUS 0x00000000ĭ (70) boot: WDT reset info: APP CPU PID 0x00000003ĭ (75) boot: WDT reset info: APP CPU PDEBUGINST 0x0e101002ĭ (81) boot: WDT reset info: APP CPU PDEBUGSTATUS 0x00000026ĭ (86) boot: WDT reset info: APP CPU PDEBUGDATA 0xaacb95f0ĭ (92) boot: WDT reset info: APP CPU PDEBUGPC 0x7677c9cfĭ (97) boot: WDT reset info: APP CPU PDEBUGLS0STAT 0x00b0000aĭ (103) boot: WDT reset info: APP CPU PDEBUGLS0ADDR 0xc1d8b65bĭ (108) boot: WDT reset info: APP CPU PDEBUGLS0DATA 0xbe30baca
Esp32 enter deepsleep pro#
W (14) boot: WDT reset info: PRO CPU PC=0x2721c99fĭ (14) boot: WDT reset info: PRO CPU STATUS 0x00000000ĭ (16) boot: WDT reset info: PRO CPU PID 0x00000002ĭ (22) boot: WDT reset info: PRO CPU PDEBUGINST 0x0f303000ĭ (27) boot: WDT reset info: PRO CPU PDEBUGSTATUS 0x00000008ĭ (33) boot: WDT reset info: PRO CPU PDEBUGDATA 0x7f6940aaĭ (38) boot: WDT reset info: PRO CPU PDEBUGPC 0x2721c99fĭ (44) boot: WDT reset info: PRO CPU PDEBUGLS0STAT 0x00001024ĭ (49) boot: WDT reset info: PRO CPU PDEBUGLS0ADDR 0x235d859cĭ (55) boot: WDT reset info: PRO CPU PDEBUGLS0DATA 0x2467c04d W (14) boot: PRO CPU has been reset by WDT.
ULP sensor period 300s, nominally 12 sweeps Mode 11, sleeptime 5m, min ULP cycles: 12 I (36675) ff_ulp: rtc i2c2 gpio to inputs I (36675) ff_ulp: Setting DOWNLOADBOOT (gpio0) as EXT1 wakeup source I (20) boot: Enabling RNG early entropy source… I (36485) ff_ulp: rtc i2c2 gpio to inputs I (36485) ff_ulp: Setting DOWNLOADBOOT (gpio0) as EXT1 wakeup source Here are two log excerpts to show the event. But as the xtensa wakes, it sees a WDT instead.
Esp32 enter deepsleep code#
This shows the ULP is running its code loop and tries to wake the xtensa at the correct time. These gaps are always associated with a WDT reset happening at the time of the regularly scheduled wakeup. We have recently been testing the systems in warmer conditions, and have discovered occasional gaps in our sensor readings. GitHub, because the reset reason is WDT rather than TG0WDT.This is not the same problem as TG0WDT_SYS_RESET upon waking up from deepsleep if FreeRTOS unicore is enabled (IDFGH-4116) These systems have had reliable up-times of weeks to months. We have multiple systems that have been reliably going into deepsleep, performing several I2C sensor readings, and then waking the main cpu to report the readings over wifi. We are having a problem with the ESP32 waking from deep sleep.
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